VHDL语法总结
CCDV2
6月 30, 2018
就当期末前的复习好了。。
分号、逗号使用
port最后一个量不加 ;port( a: in std_logic; b: out std_logic );with-select-when(无优先级)
除了others后面为分号，其余为逗号with sel select f <= d0 when "00", d1 when "01", d2 when "10", d3 when others;
when-else(带优先级)
只有最后一个有 ;
没有otherstemp <= "000" when I(7) = '0' else "001" when I(6) = '0' else "010" when I(5) = '0' else "011" when I(4) = '0' else "100" when I(3) = '0' else "101" when I(2) = '0' else "110" when I(1) = '0' else "111";
if-else
没啥好说的if then end if; if then else end if; if then elsif then end if;
case-whencase temp is when "00" => z <= d0; when "01" => z <= d1; when "10" => z <= d2; when other => z <= d3;end ???
entity 和 architecture 后面end自己起的
process 后面end processbegin
architecture process 后加begin在process中赋值
对于变量
:= 即时有效
对于信号
<= 在信号结束之后赋值
因此，不要在process中对一个信号多次赋值
process (a, b, c) variable d: std_logic; begin d := a; x <= c and d; -- x <= c and a d := b; y <= c and d; -- y <= c and b end process;自定义类型type
type week is (sun, mon, tue, wed, thu, fri, sat); signal day : week;
这鬼畜的高亮。。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dianzizhong is
port(
clr: in std_logic;
clk: in std_logic;
pause: in std_logic;
reverse: in std_logic;
led2: out std_logic_vector (6 downto 0);
led1, led3, led4, led5, led6: out std_logic_vector (3 downto 0)
);
end dianzizhong;
architecture func of dianzizhong is
signal ten, one: std_logic_vector (3 downto 0);
signal secondToMinute, minuteToHour: std_logic;
signal mten, mone: std_logic_vector (3 downto 0);
signal hten, hone: std_logic_vector (3 downto 0);
begin
process(clk, clr)
begin
if clr = '1' then
ten <= "0000";
one <= "0000";
elsif clk'event and clk = '1' then
if pause = '1' then
else
if reverse = '0' then
if one = 9 then
if ten = 5 then
ten <= "0000";
one <= "0000";
secondToMinute <= '1';
else
ten <= ten + 1;
one <= "0000";
secondToMinute <= '0';
end if;
else
one <= one + 1;
secondToMinute <= '0';
end if;
else
if one = 0 then
if ten = 0 then
ten <= "0101";
one <= "1001";
secondToMinute <= '1';
else
ten <= ten - 1;
one <= "1001";
secondToMinute <= '0';
end if;
else
one <= one - 1;
secondToMinute <= '0';
end if;
end if;
end if;
end if;
end process;
process(secondToMinute, clr)
begin
if clr = '1' then
mten <= "0000";
mone <= "0000";
elsif secondToMinute'event and secondToMinute = '1' then
if pause = '1' then
else
if reverse = '0' then
if mone = 9 then
if mten = 5 then
mten <= "0000";
mone <= "0000";
minuteToHour <= '1';
else
mten <= mten + 1;
mone <= "0000";
minuteToHour <= '0';
end if;
else
mone <= mone + 1;
minuteToHour <= '0';
end if;
else
if mone = 0 then
if mten = 0 then
mten <= "0101";
mone <= "1001";
minuteToHour <= '1';
else
mten <= mten - 1;
mone <= "1001";
minuteToHour <= '0';
end if;
else
mone <= mone - 1;
minuteToHour <= '0';
end if;
end if;
end if;
end if;
end process;
process(minuteToHour, clr)
begin
if clr = '1' then
hten <= "0000";
hone <= "0000";
elsif minuteToHour'event and minuteToHour = '1' then
if pause = '1' then
else
if reverse = '0' then
if hone = 1 then
if hten = 1 then
hten <= "0000";
hone <= "0000";
else
hten <= hten + 1;
hone <= "0000";
end if;
else
hone <= hone + 1;
end if;
else
if hone = 0 then
if hten = 0 then
hten <= "0001";
hone <= "0001";
else
hten <= hten - 1;
hone <= "1001";
end if;
else
hone <= hone - 1;
end if;
end if;
end if;
end if;
end process;
led1 <= ten;
led3 <= mone;
led4 <= mten;
led5 <= hone;
led6 <= hten;
with one select
led2 <= "1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"0011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110011" when "1001",
"0000000" when others;
end func;